Objective
2005 California Vehicle Code Sections 7 CHAPTER 4. RIGHT-OF-WAY VEHICLE CODE SECTION 7 21800. (a) The driver of a vehicle approaching an intersection shall yield the right-of-way to any vehicle which has entered the intersection from a different highway.
Design a digital controller to control traffic at an intersection of a busy main street (North-South) and an occasionally used side street (East-West).
- North South must be Green for a minimum of 25 seconds and will remain Green until traffic is present on East-West
- East West will remain Green for a maximum of 25 seconds
- Yellow lights on both streets must be for 4 seconds
This project includes a presentation detailing the thought process and application of this implementation of a traffic light controller. [PDF] Project 3 Presentation
Waveforms
Simulation results from test A of the Traffic Light Controller module (No traffic on either NS or EW)
Simulation results from test B of the Traffic Light Controller module (Steady traffic on both NS and EW)
![Controller Controller](/uploads/1/2/5/5/125557929/420965253.jpg)
Simulation results from test C of the Traffic Light Controller module (Steady traffic on NS, not EW)
Simulation results from test D of the Traffic Light Controller module (Steady traffic on EW, not NS)
Simulation results from test E of the Traffic Light Controller module (Intermittent traffic on NS, none on EW)
Simulation results from test F of the Traffic Light Controller module (Intermittent traffic on EW, none on NS)
Simulation results from test G of the Traffic Light Controller module (Intermittent traffic on both NS and EW, e.g. 1 car every 20 or 30 seconds)
Simulation results from test H of the Traffic Light Controller module (Constant ongoing traffic detected on both NS and EW)
Source Files
![Code Code](http://i.ytimg.com/vi/bjqYvTvY1Qg/maxresdefault.jpg)
- Traffic Control Module - Traffic_eng312_proj3.v
- Traffic Control Test Bench A - Traffic_Test_A_eng312_proj3.v
- Traffic Control Test Bench B - Traffic_Test_B_eng312_proj3.v
- Traffic Control Test Bench C - Traffic_Test_C_eng312_proj3.v
- Traffic Control Test Bench D - Traffic_Test_D_eng312_proj3.v
- Traffic Control Test Bench E - Traffic_Test_E_eng312_proj3.v
- Traffic Control Test Bench F - Traffic_Test_F_eng312_proj3.v
- Traffic Control Test Bench G - Traffic_Test_G_eng312_proj3.v
- Traffic Control Test Bench H - Traffic_Test_H_eng312_proj3.v
- A Mealy Finite State Machine (FSM), developed in Verilog, designed to control traffic lights at a crossroad having a major road (main road) and a minor road (side road).
- The main road's lights are always green for the major traffic to pass.
- The main road's lights turn red only when there is a car on either side of the main road i.e. on the side road.
- The controller waits for a car to be present on the side road for a period of time, only then the lights of the side road turn from red->green while the main road's lights turn from green->yellow->red.
- Side road lights turn from green->yellow->red after a specified period of time, even if there are other cars on the side road, while the main road's lights turn from red->green.
- All the timings are controlled by a single custom built synchronous MOD16 timer.
- This timer is configurable and is capable of indicating the end of count at variable times.
- Configurability of the timer keeps the design smaller than other approaches that typically use several counters for different timing purposes in such a system.
Modules and their functionalities
lightfsmj.v
: Contains the FSM i.e. the main controller of the traffic lightstimer.v
: Contains the configurable timer moduletop.v
: Combines the FSM and the timer to build the smart traffic light systemtestbench.v
: Contains the test cases that were vital to test the functionality of this systemtop.sdf
: The constraints file extracted from Design Compiler after synthesis. This file contains delay information of each cell that is in the designfinal_script.scr
: Contains commands to:- process the project from source code to synthesized netlist
- extract .sdf file
- create report for:
- Timing of the system
- Area of the synthesized system
- Power utilization of the design
- Cell information
Language used
- Verilog: C like HDL is easier to comprehend and saves design time since the syntax is more concise that VHDL
Tools used
- Cadence NCSim: To compile and check logic design
- Synopsys Design Compiler: To obtain the synthesized netlist from the design
Group Members
- Raashid Ansari - Timer Designer, Coder, Testbench coder
- William Nitsch - Timer Designer, Coder, and Team Lead
- Jonathan Frey - FSM Designer, coder
NOTE: Refer to [report](group report smart traffic light controller.pdf 'group report stepper motor fsm.pdf') for detailed explanation of the project.